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Compatible Systems RISC 2800i Manual de usuario Pagina 17

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MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4
Freescale Semiconductor 17
Electrical and Thermal Characteristics
Figure 3 provides the SYSCLK input timing diagram.
Figure 3. SYSCLK Input Timing Diagram
5.2.2 Processor Bus AC Specifications
Table 9 provides the processor bus AC timing specifications for the MPC7448 as defined in Figure 4 and
Figure 5.
Table 9. Processor Bus AC Timing Specifications
1
At recommended operating conditions. See Table 4.
Parameter Symbol
2
All Speed Grades
Unit Notes
Min Max
Input setup times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK
, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL, TT[0:4],
QACK
, TA, TBEN, TEA, TS, EXT_QUAL, PMON_IN,
SHD
[0:1]
BMODE
[0:1], BVSEL[0:1]
t
AVKH
t
DVKH
t
IVKH
t
MVKH
1.5
1.5
1.5
1.5
—
—
—
—
ns
—
—
—
8
Input hold times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK
, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL, TT[0:4],
QACK
, TA, TBEN, TEA, TS, EXT_QUAL, PMON_IN,
SHD
[0:1]
BMODE
[0:1], BVSEL[0:1]
t
AXKH
t
DXKH
t
IXKH
t
MXKH
0
0
0
0
—
—
—
—
ns
—
—
—
—
8
Output valid times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
BR
, CI, DRDY, GBL, HIT, PMON_OUT, QREQ, TBST,
TSIZ[0:2], TT[0:4], WT
TS
ARTRY, SHD[0:1]
t
KHAV
t
KHDV
t
KHOV
t
KHTSV
t
KHARV
—
—
—
—
—
1.8
1.8
1.8
1.8
1.8
ns
Output hold times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
BR
, CI, DRDY, GBL, HIT, PMON_OUT, QREQ, TBST,
TSIZ[0:2], TT[0:4], WT
TS
ARTRY, SHD[0:1]
t
KHAX
t
KHDX
t
KHOX
t
KHTSX
t
KHARX
0.5
0.5
0.5
0.5
0.5
—
—
—
—
—
ns
SYSCLK to output enable t
KHOE
0.5 — ns 5
SYSCLK
V
M
V
M
V
M
CV
IH
CV
IL
V
M
= Midpoint Voltage (OV
DD
/2)
t
SYSCLK
t
KR
t
KF
t
KHKL
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