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MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

50 Freescale Semiconductor

System Design Information

The ratio of I

to I

is usually selected to be 10:1. The above simplifies to the following:

Solving for T, the equation becomes:

9.8.5 Dynamic Frequency Switching (DFS)

The new DFS feature in the MPC7447A adds the ability to divide the processor-to-system bus ratio by two

during normal functional operation by setting the HID1[DFS2] bit. The frequency change occurs in 1 clock

cycle, and no idle waiting period is required to switch between modes. Additional information regarding

DFS can be found in the MPC7450 RISC Microprocessor Family Reference Manual.

9.8.5.1 Power Consumption with DFS Enabled

Power consumption with DFS enabled can be approximated using the following formula:

Where:

DFS

= Power consumption with DFS enabled

DFS

= Core frequency with DFS enabled

f = Core frequency prior to enabling DFS

P = Power consumption prior to enabling DFS (see Table 7)

= Deep sleep mode power consumption (see Table 7)

The above is an approximation only. Power consumption with DFS enabled is not tested or guaranteed.

9.8.5.2 Bus-to-Core Multiplier Constraints with DFS

DFS is not available for all bus-to-core multipliers as configured by PLL_CFG[0:4] during hard reset.

Specifically, because the MPC7447A does not support quarter clock ratios or the 1x multiplier, the DFS

feature is limited to integer PLL multipliers of 4x and higher. The complete listing is shown in Table 16.

Table 16. Valid Divide Ratio Configurations

Bus-to-Core Multiplier Configured

by PLL_CFG[0:4]

(see Table 13)

Bus-to-Core Multiplier with

HID1[DFS1] = 1

(

÷2)

2x N/A

3x N/A

– V

= 1.986 × 10

-4

× nT

nT =

– V

__________

1.986 × 10

-4

DFS

= (P– P

) + P

DFS

___

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